Got rid of the MMX instructions in the SSE version of the code. Handling the mask operations in a class, which is defined for each version of SSE and AVX implementations separately.
This commit is contained in:
mozdal
parent
7180c392af
commit
0170d4f3d5
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@ -16,3 +16,4 @@
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template double compute_full_prob_avxd<double>(testcase* tc, double* nextlog);
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template float compute_full_prob_avxs<float>(testcase* tc, float* nextlog);
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@ -47,6 +47,7 @@
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#undef MASK_ALL_ONES
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#undef COMPARE_VECS(__v1, __v2)
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#undef _256_INT_TYPE
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#undef BITMASK_VEC
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#endif
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#define PRECISION d
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@ -156,3 +157,32 @@
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} \
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} \
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}
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class BitMaskVec_double {
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MASK_VEC low_, high_ ;
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_256_TYPE combined_ ;
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public:
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inline MASK_TYPE& getLowEntry(int index) {
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return low_.masks[index] ;
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}
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inline MASK_TYPE& getHighEntry(int index) {
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return high_.masks[index] ;
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}
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inline const _256_TYPE& getCombinedMask() {
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VEC_SSE_TO_AVX(low_.vecf, high_.vecf, combined_) ;
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return combined_ ;
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}
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inline void shift_left_1bit() {
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VEC_SHIFT_LEFT_1BIT(low_.vec) ;
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VEC_SHIFT_LEFT_1BIT(high_.vec) ;
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}
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} ;
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#define BITMASK_VEC BitMaskVec_double
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@ -47,6 +47,7 @@
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#undef MASK_ALL_ONES
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#undef COMPARE_VECS(__v1, __v2)
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#undef _256_INT_TYPE
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#undef BITMASK_VEC
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#endif
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#define PRECISION s
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@ -157,3 +158,31 @@
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} \
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}
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class BitMaskVec_float {
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MASK_VEC low_, high_ ;
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_256_TYPE combined_ ;
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public:
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inline MASK_TYPE& getLowEntry(int index) {
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return low_.masks[index] ;
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}
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inline MASK_TYPE& getHighEntry(int index) {
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return high_.masks[index] ;
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}
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inline const _256_TYPE& getCombinedMask() {
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VEC_SSE_TO_AVX(low_.vecf, high_.vecf, combined_) ;
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return combined_ ;
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}
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inline void shift_left_1bit() {
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VEC_SHIFT_LEFT_1BIT(low_.vec) ;
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VEC_SHIFT_LEFT_1BIT(high_.vec) ;
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}
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} ;
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#define BITMASK_VEC BitMaskVec_float
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@ -47,7 +47,7 @@
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#undef MASK_ALL_ONES
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#undef COMPARE_VECS(__v1, __v2)
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#undef _256_INT_TYPE
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#undef BITMASK_VEC
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#endif
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#define SSE
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@ -69,7 +69,7 @@
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#define HAP_TYPE __m128i
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#define MASK_TYPE uint64_t
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#define MASK_ALL_ONES 0xFFFFFFFFFFFFFFFFL
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#define MASK_VEC MaskVec_D128
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#define MASK_VEC MaskVec_D
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#define VEC_EXTRACT_UNIT(__v1, __im) \
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_mm_extract_epi64(__v1, __im)
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@ -123,6 +123,31 @@
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__vdst = _mm_castsi128_pd(_mm_set_epi64(__vsHigh, __vsLow))
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#define VEC_SHIFT_LEFT_1BIT(__vs) \
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__vs = _mm_slli_si64(__vs, 1)
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__vs = _mm_slli_epi64(__vs, 1)
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class BitMaskVec_sse_double {
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MASK_VEC combined_ ;
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public:
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inline MASK_TYPE& getLowEntry(int index) {
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return combined_.masks[index] ;
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}
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inline MASK_TYPE& getHighEntry(int index) {
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return combined_.masks[AVX_LENGTH/2+index] ;
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}
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inline const _256_TYPE& getCombinedMask() {
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return combined_.vecf ;
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}
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inline void shift_left_1bit() {
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VEC_SHIFT_LEFT_1BIT(combined_.vec) ;
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}
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} ;
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#define BITMASK_VEC BitMaskVec_sse_double
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@ -47,7 +47,7 @@
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#undef MASK_ALL_ONES
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#undef COMPARE_VECS(__v1, __v2)
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#undef _256_INT_TYPE
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#undef BITMASK_VEC
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#endif
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#define SSE
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@ -69,7 +69,7 @@
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#define HAP_TYPE UNION_TYPE
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#define MASK_TYPE uint32_t
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#define MASK_ALL_ONES 0xFFFFFFFF
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#define MASK_VEC MaskVec_F128
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#define MASK_VEC MaskVec_F
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#define VEC_EXTRACT_UNIT(__v1, __im) \
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_mm_extract_epi32(__v1, __im)
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@ -123,5 +123,29 @@
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__vdst = _mm_cvtpi32x2_ps(__vsLow, __vsHigh)
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#define VEC_SHIFT_LEFT_1BIT(__vs) \
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__vs = _mm_slli_pi32(__vs, 1)
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__vs = _mm_slli_epi32(__vs, 1)
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class BitMaskVec_sse_float {
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MASK_VEC combined_ ;
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public:
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inline MASK_TYPE& getLowEntry(int index) {
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return combined_.masks[index] ;
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}
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inline MASK_TYPE& getHighEntry(int index) {
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return combined_.masks[AVX_LENGTH/2+index] ;
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}
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inline const _256_TYPE& getCombinedMask() {
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return combined_.vecf ;
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}
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inline void shift_left_1bit() {
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VEC_SHIFT_LEFT_1BIT(combined_.vec) ;
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}
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} ;
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#define BITMASK_VEC BitMaskVec_sse_float
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@ -19,6 +19,12 @@ LoadTimeInitializer g_load_time_initializer;
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#define BATCH_SIZE 10000
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#define RUN_HYBRID
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double getCurrClk() {
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struct timeval tv ;
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gettimeofday(&tv, NULL);
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return (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
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}
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int main(int argc, char** argv)
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{
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if(argc < 2)
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@ -29,6 +35,10 @@ int main(int argc, char** argv)
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bool use_old_read_testcase = false;
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if(argc >= 3 && string(argv[2]) == "1")
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use_old_read_testcase = true;
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unsigned chunk_size = 100;
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if(argc >= 4)
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chunk_size = strtol(argv[3],0,10);
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initialize_function_pointers();
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@ -45,12 +55,24 @@ int main(int argc, char** argv)
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assert(ifptr.is_open());
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}
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vector<testcase> tc_vector;
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tc_vector.clear();
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testcase tc;
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while(1)
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{
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int break_value = use_old_read_testcase ? read_testcase(&tc, fptr) : read_mod_testcase(ifptr,&tc,true);
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if(break_value < 0)
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break;
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tc_vector.push_back(tc);
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}
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vector<double> results_vec;
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results_vec.clear();
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results_vec.resize(tc_vector.size());
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double start_time = getCurrClk();
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#pragma omp parallel for schedule(dynamic,chunk_size) num_threads(12)
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for(unsigned i=0;i<tc_vector.size();++i)
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{
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testcase& tc = tc_vector[i];
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float result_avxf = g_compute_full_prob_float(&tc, 0);
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double result = 0;
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if (result_avxf < MIN_ACCEPTED) {
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@ -60,12 +82,23 @@ int main(int argc, char** argv)
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else
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result = (double)(log10f(result_avxf) - log10f(ldexpf(1.f, 120.f)));
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results_vec[i] = result;
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}
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cout << "Time taken "<<getCurrClk()-start_time << "\n";
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for(unsigned i=0;i<tc_vector.size();++i)
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{
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testcase& tc = tc_vector[i];
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double baseline_result = compute_full_prob<double>(&tc);
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baseline_result = log10(baseline_result) - log10(ldexp(1.0, 1020.0));
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cout << std::scientific << baseline_result << " "<<result<<"\n";
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delete tc.rs;
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delete tc.hap;
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double abs_error = fabs(baseline_result-results_vec[i]);
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double rel_error = (baseline_result != 0) ? fabs(abs_error/baseline_result) : 0;
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if(abs_error > 1e-5 && rel_error > 1e-5)
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cout << std::scientific << baseline_result << " "<<results_vec[i]<<"\n";
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delete tc_vector[i].rs;
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delete tc_vector[i].hap;
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}
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results_vec.clear();
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tc_vector.clear();
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if(use_old_read_testcase)
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fclose(fptr);
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else
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@ -23,6 +23,7 @@ string getBinaryStr (T val, int numBitsToWrite) {
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*/
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#ifdef MUSTAFA
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void GEN_INTRINSIC(GEN_INTRINSIC(precompute_masks_,SIMD_TYPE), PRECISION)(const testcase& tc, int COLS, int numMaskVecs, MASK_TYPE (*maskArr)[NUM_DISTINCT_CHARS]) {
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const int maskBitCnt = MAIN_TYPE_SIZE ;
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@ -77,28 +78,25 @@ void GEN_INTRINSIC(GEN_INTRINSIC(init_masks_for_row_,SIMD_TYPE), PRECISION)(cons
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}
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void GEN_INTRINSIC(GEN_INTRINSIC(update_masks_for_cols_, SIMD_TYPE), PRECISION)(int maskIndex, MASK_VEC& currMaskVecLow, MASK_VEC& currMaskVecHigh, MASK_TYPE (*maskArr) [NUM_DISTINCT_CHARS], char* rsArr, MASK_TYPE* lastMaskShiftOut, MASK_TYPE maskBitCnt) {
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void GEN_INTRINSIC(GEN_INTRINSIC(update_masks_for_cols_, SIMD_TYPE), PRECISION)(int maskIndex, BITMASK_VEC& bitMaskVec, MASK_TYPE (*maskArr) [NUM_DISTINCT_CHARS], char* rsArr, MASK_TYPE* lastMaskShiftOut, int maskBitCnt) {
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for (int ei=0; ei < AVX_LENGTH/2; ++ei) {
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SET_MASK_WORD(currMaskVecLow.masks[ei], maskArr[maskIndex][rsArr[ei]],
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SET_MASK_WORD(bitMaskVec.getLowEntry(ei), maskArr[maskIndex][rsArr[ei]],
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lastMaskShiftOut[ei], ei, maskBitCnt) ;
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int ei2 = ei + AVX_LENGTH/2 ; // the second entry index
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SET_MASK_WORD(currMaskVecHigh.masks[ei], maskArr[maskIndex][rsArr[ei2]],
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SET_MASK_WORD(bitMaskVec.getHighEntry(ei), maskArr[maskIndex][rsArr[ei2]],
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lastMaskShiftOut[ei2], ei2, maskBitCnt) ;
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}
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}
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//void GEN_INTRINSIC(computeDistVec, PRECISION) (MASK_VEC& currMaskVecLow, MASK_VEC& currMaskVecHigh, _256_TYPE& distm, _256_TYPE& _1_distm, _256_TYPE& distmChosen, const _256_TYPE& distmSel, int firstRowIndex, int lastRowIndex) {
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//void GEN_INTRINSIC(computeDistVec, PRECISION) (BITMASK_VEC& bitMaskVec, _256_TYPE& distm, _256_TYPE& _1_distm, _256_TYPE& distmChosen, const _256_TYPE& distmSel, int firstRowIndex, int lastRowIndex) {
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inline void GEN_INTRINSIC(GEN_INTRINSIC(computeDistVec, SIMD_TYPE), PRECISION) (MASK_VEC& currMaskVecLow, MASK_VEC& currMaskVecHigh, _256_TYPE& distm, _256_TYPE& _1_distm, _256_TYPE& distmChosen) {
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inline void GEN_INTRINSIC(GEN_INTRINSIC(computeDistVec, SIMD_TYPE), PRECISION) (BITMASK_VEC& bitMaskVec, _256_TYPE& distm, _256_TYPE& _1_distm, _256_TYPE& distmChosen) {
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//#define computeDistVec() {
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_256_TYPE maskV ;
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VEC_SSE_TO_AVX(currMaskVecLow.vecf, currMaskVecHigh.vecf, maskV) ;
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#ifdef DEBUGG
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long long *temp1 = (long long *)(&maskV);
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double *temp2 = (double *)(&distm);
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@ -106,14 +104,11 @@ inline void GEN_INTRINSIC(GEN_INTRINSIC(computeDistVec, SIMD_TYPE), PRECISION) (
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printf("***\n%lx\n%lx\n%f\n%f\n%f\n%f\n***\n", temp1[0], temp1[1], temp2[0], temp2[1], temp3[0], temp3[1]);
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#endif
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distmChosen = VEC_BLENDV(distm, _1_distm, maskV) ;
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distmChosen = VEC_BLENDV(distm, _1_distm, bitMaskVec.getCombinedMask()) ;
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/*COMPARE_VECS(distmChosen, distmSel, firstRowIndex, lastRowIndex) ;*/
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VEC_SHIFT_LEFT_1BIT(currMaskVecLow.vec) ;
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VEC_SHIFT_LEFT_1BIT(currMaskVecHigh.vec) ;
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_mm_empty();
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bitMaskVec.shift_left_1bit() ;
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}
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@ -347,15 +342,16 @@ template<class NUMBER> NUMBER GEN_INTRINSIC(GEN_INTRINSIC(compute_full_prob_,SIM
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GEN_INTRINSIC(GEN_INTRINSIC(init_masks_for_row_,SIMD_TYPE), PRECISION)(*tc, rsArr, lastMaskShiftOut, i*AVX_LENGTH+1, AVX_LENGTH) ;
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#endif
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// Since there are no shift intrinsics in AVX, keep the masks in 2 SSE vectors
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MASK_VEC currMaskVecLow ; // corresponding to lower half
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MASK_VEC currMaskVecHigh ; // corresponding to upper half
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BITMASK_VEC bitMaskVec ;
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for (int d=1;d<COLS+AVX_LENGTH;d++)
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{
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#ifdef MUSTAFA
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if (d % MAIN_TYPE_SIZE == 1)
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GEN_INTRINSIC(GEN_INTRINSIC(update_masks_for_cols_,SIMD_TYPE), PRECISION)((d-1)/MAIN_TYPE_SIZE, currMaskVecLow, currMaskVecHigh, maskArr, rsArr, lastMaskShiftOut, maskBitCnt) ;
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GEN_INTRINSIC(GEN_INTRINSIC(computeDistVec,SIMD_TYPE), PRECISION) (currMaskVecLow, currMaskVecHigh, distm, _1_distm, distmChosen) ;
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GEN_INTRINSIC(GEN_INTRINSIC(update_masks_for_cols_,SIMD_TYPE), PRECISION)((d-1)/MAIN_TYPE_SIZE, bitMaskVec, maskArr, rsArr, lastMaskShiftOut, maskBitCnt) ;
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GEN_INTRINSIC(GEN_INTRINSIC(computeDistVec,SIMD_TYPE), PRECISION) (bitMaskVec, distm, _1_distm, distmChosen) ;
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#else
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distmChosen = GEN_INTRINSIC(GEN_INTRINSIC(computeDISTM,SIMD_TYPE), PRECISION)(d, COLS, tc, hap, rs.d, rsN, N_packed256, distm, _1_distm);
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#endif
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@ -391,15 +387,14 @@ template<class NUMBER> NUMBER GEN_INTRINSIC(GEN_INTRINSIC(compute_full_prob_,SIM
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sumX = VEC_SET1_VAL(zero);
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// Since there are no shift intrinsics in AVX, keep the masks in 2 SSE vectors
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MASK_VEC currMaskVecLow ; // corresponding to lower half
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MASK_VEC currMaskVecHigh ; // corresponding to upper half
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BITMASK_VEC bitMaskVec ;
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for (int d=1;d<COLS+remainingRows-1;d++)
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{
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#ifdef MUSTAFA
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if (d % MAIN_TYPE_SIZE == 1)
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GEN_INTRINSIC(GEN_INTRINSIC(update_masks_for_cols_, SIMD_TYPE),PRECISION)((d-1)/MAIN_TYPE_SIZE, currMaskVecLow, currMaskVecHigh, maskArr, rsArr, lastMaskShiftOut, maskBitCnt) ;
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GEN_INTRINSIC(GEN_INTRINSIC(computeDistVec, SIMD_TYPE), PRECISION) (currMaskVecLow, currMaskVecHigh, distm, _1_distm, distmChosen) ;
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GEN_INTRINSIC(GEN_INTRINSIC(update_masks_for_cols_, SIMD_TYPE),PRECISION)((d-1)/MAIN_TYPE_SIZE, bitMaskVec, maskArr, rsArr, lastMaskShiftOut, maskBitCnt) ;
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GEN_INTRINSIC(GEN_INTRINSIC(computeDistVec, SIMD_TYPE), PRECISION) (bitMaskVec, distm, _1_distm, distmChosen) ;
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#else
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distmChosen = GEN_INTRINSIC(GEN_INTRINSIC(computeDISTM,SIMD_TYPE), PRECISION)(d, COLS, tc, hap, rs.d, rsN, N_packed256, distm, _1_distm);
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#endif
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@ -35,8 +35,7 @@ bool is_sse42_supported()
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void initialize_function_pointers()
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{
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//if(is_avx_supported())
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if(false)
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if(0 && is_avx_supported())
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{
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cout << "Using AVX accelerated implementation of PairHMM\n";
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g_compute_full_prob_float = compute_full_prob_avxs<float>;
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@ -17,6 +17,7 @@
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#define SIMD_TYPE sse
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#define SIMD_TYPE_SSE
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#include "define-sse-float.h"
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#include "vector_function_prototypes.h"
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